In the standard methods of testing ASIC integrated circuits, the circuit contains test structures that supply a scan vector to the operating components, which process that data. The result of the processing of the scan vector is then compared against the expected values to see if the part passes or fails.
In addition to supplying a scan vector of data for the circuit to operate on, the testing setup also supplies a set of clock signals. In various test modes, non-standard clock pulses may be required. The required clock signal may be a short pulse train, a single pulse, a single edge of a clock pulse (rising or falling) or a DC level, high or low.
Integrated circuits often have different clock domains that use clock signals that may differ in phase and/or frequency. The invention enables an at speed structural test of logic using the functional clock. The invention does not depend on a particular scan style such as Mux-Scan or LSSD.
In typical design practices, the components of the clock distribution signals for test clocks are not as fast as the comparable distribution system for functional (those used in normal operation) clocks, so that it is not possible to perform an “at speed” test; i.e. at normal operating speed. Evidently, there may be a problem in a circuit that operates correctly at a reduced test speed, but not at the normal operating speed.
The art could use a flexible system for performing a test at the functional speed. In addition the art could use a flexible system for testing the logic paths between 2 related synchronous clock domains. The invention enables a method of testing such paths.
The art could use a clock control system which does not require at speed timing closure. The invention as illustrated relaxes timing requirements so that at least an additional one half cycle of margin is built in.